This invention relates to a method of fabricating semiconductor integrated circuit devices, and, more particularly, to techniques for self-aligning an isolating region in a semiconductor integrated circuit device with semiconductor regions formed on islands (active regions) surrounded by the isolating region.
Among the isolation methods for forming a plurality of dielectrically isolated islands, on which circuit elements are to be formed, on a silicon semiconductor body in a bipolar type integrated circuit device, the oxide isolation method is widely used. In the oxide isolation method, an oxidation impermeable mask consisting of silicon nitride film is formed to cover the parts of a semiconductor body which are to become islands, and the semiconductor body is then exposed to an oxidizing atmosphere to form a thick oxide film (field oxide film), which constitutes the isolating region.
The oxide isolation method has a disadvantage in that a part of the thick isolation oxide film over the surface of each island projects like a bird's beak. Accordingly, when impurities are diffused into an island by using as a mask a thick oxide film that has a bird's beak to form a PN junction such as a collector-base junction, the part of the PN junction which is located at a boundary between the thick oxide film and the island is covered with a thinner oxide film in the shape of the bird's beak. Consequently, when the resultant product is subjected to an oxide film-removing step, for example, a washing step, after a first PN junction has been formed, a part of the thin oxide film in the shape of the bird's beak is removed, so that the PN junction formed by using the bird beak part as a mask is uncovered from the oxide film or is nearly uncovered. As a result, when a second type of impurity is then introduced into, or when an electrode is then formed on, the resultant product by utilizing the thick oxide film as part of a mask, the initially-formed PN junction is short-circuited.
In a conventional technique for forming a bipolar transistor by using the oxide isolation methid, the base diffusion is carried out by utilizing an oxide isolation film having a bird's beak as a mask. However, the emitter diffusion, which is carried out by utilizing the oxide isolation mask, it not employed in the next step since it is liable to cause a short-circuit between the emitter and collector. The step of forming a so-called walled emitter structure by carrying out the diffusion of an emitter region with an oxide isolation film utilized as part of a mask is not employed. In fact, an emitter region is formed in the central part of an island, which is separated from the isolation oxide film by a predetermined distance. In order to form an emitter region in a position separated from a bird's beak, it is necessary to determine the distance between the dielectric isolating region and the emitter-forming region, taking into consideration any errors occurring in the alignment of the mask for the emitter-forming region with that for the dielectric isolating region. Mask-alignment errors cannot be ignored in the current mask-alignment techniques. Accordingly, it is necessary that the area of the semiconductor body which is used to form transistors thereon is increased. The above problems will be described hereinafter with reference to the drawings so as to make the problems easier to understand.
As shown in FIGS. 1A and 1B, a thick oxide film (field oxide film) 4, which is formed by thermally oxidizing a semiconductor body 1, is used as a dielectric isolating region in each semiconductor region. It is necessary in this case that no so-called "walled emitter structures," in which the field oxide film 4 and an emitter region 7 overlap each other, are formed. The reasons why the formation of a walled emitter structure should be avoided are as follows:
If a walled emitter structure is formed, short-circuiting could occur between an emitter and a collector as mentioned above, and a sufficiently high breakdown voltage between adjacent transistor elements cannot be obtained.
In order to prevent a walled emitter structure from being formed, it is necessary to leave a mask-alignment margin to allow for any errors occurring in the alignment of the mask defining the field oxide film 4 with the mask defining the emitter region 7. For example, if the distance d.sub.1, by which the field oxide film 4 and emitter region 7 shown in FIG. 1A should be separated, must be 3 .mu.m, the distance d.sub.1 is made 4.5 .mu.m in practice, to include a margin corresponding to an error of .+-.1.5 .mu.m occurring in the alignment of the masks, to secure the required distance of 3 .mu.m irrespective of the degree of mask-alignment error.
When a mask-alignment margin is left in the above manner, any short-circuiting, which could occur due to a walled emitter structure forming, can be prevented. However, on the other hand, leaving a margin in such a manner raises the following problems.
Providing a mask-alignment margin between the field oxide film 4 and the emitter region 7 causes an increase in the area of the base region and an increase in the area of a base-collector junction as may be clearly understood from the drawings. Thus, leaving a mask-alignment margin prevents an increase in the degree of integration of the semiconductor integrated circuit device, and causes an increase in the collector-base junction capacitance, which inhibits the high-speed operation of a semiconductor integrated device. The above results have given rise to some problems as the techniques for increasing the degree of integration and the speed of operation of ICs has advanced in recent years.